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¥°. ¼ ·Ð ¥±. º» ·Ð 1. VRML ( Virtual Reality Modeling Language ) Á¤ÀÇ 2. VRMLÀÇ ¿ª»ç ¹× µîÀå¹è°æ 3. VRMLÀÇ Æ¯Â¡µé 4. VRMLÀÇ ÀÀ¿ëºÐ¾ß 5. VRMLÀÇ ¼³°è ¹üÁÖ 6. VRMLÀÇ ±âº»ÀÌ µÇ´Â ³»¿ëµé 7. VRMLÀÇ ³»¿ëÀÛ¼º 8. VRML ºê¶ó¿ìÁ® ¥². °á ·Ð 1. VRMLÀÇ Àü¸Á FileSize : 58K / ¥°. ¼ ·Ð ¥±. º» ·Ð 1. VRML ( Virtual Reality Modeling Language ) Á¤ÀÇ 2. VR¡¦
°øÇбâ¼ú  | 
16p
age  
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1,700 ¿ø
Æí¹ÌºÐ¹æÁ¤½Ä modeling(Navier-stokes)¿¡ ´ëÇÑ ³»¿ëÀÔ´Ï´Ù. / 1. ÀÌ·ÐÀû ¹è°æ 2. Navier-Stokes equations modeling 3. Æí¹ÌºÐ¹æÁ¤½Ä Ç®ÀÌ(in detail) & °æ°èÁ¶°Ç and/or ÃʱâÁ¶°Ç ¼³Á¤ 4. ÇØ¿¡ ´ëÇÑ °øÇÐÀû Çؼ® / ÀÌ·ÐÀû ¹è°æ ³ªºñ¿¡-½ºÅäÅ©½º ¹æÁ¤½Ä(Navier-Stokes equations)´Â Á¡¼ºÀ» °¡Áø À¯Ã¼ÀÇ ¿îµ¿À» ±â¼úÇÏ´Â ºñ¼±Çü Æí¹ÌºÐ ¹æÁ¤½ÄÀÌ´Ù. ÇÁ¶û½º ¹°¸®ÇÐÀÚ Claude-Louis Navier¡¦
°øÇбâ¼ú  | 
9p
age  
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3,000 ¿ø
spice, cmm, nolan stage model ºñ±³ / 1. SPICE SPICE ´Â ¼ÒÇÁÆ®¿þ¾î ÇÁ·Î¼¼½º ½É»ç(SPA) Ç¥ÁØÀÎ ISO/IEC 15504¸¦ °³¹ßÇÏ¿© ¹ß°£Çϱâ À§ÇØ ÇöÀç ISO/IEC JTC1 SC7 WG10 ¿¡¼ ÃßÁøÁßÀÎ ÇÁ·ÎÁ§Æ®ÀÌ´Ù. JTC1¡¦
°øÇбâ¼ú  | 
15p
age  
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2,000 ¿ø
¡¥ which is the abbreviation of model, view, and controller, is related to the design. MVC is very efficient and effective form of design pattern. Programmers have realized that MVC design pattern is proper for developing, revising, improving and managing the software, especially GUI software. The basic concept of MVC is that dividing the software into three¡¦
°øÇбâ¼ú  | 
5p
age  
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1,500 ¿ø
[°øÇÐ] »çÁøÃø·® - Digital Elevation Model[DEM]¿¡ °üÇÑ Á¶»ç / »çÁøÃø·® Report - Digital Elevation Model(DEM)¿¡ °üÇÑ Á¶»ç - ¸ñ Â÷ 1. DEM(digital elevation model)ÀÇ Á¤ÀÇ 1 http://en.wikipedia.org/wiki/Digital_elevation_model 2. DEM ÀÚ·áÀÇ À¯Çü¿¡ µû¸¥ Àå´ÜÁ¡ 2 http://www.macaulay.ac.uk/LADSS/documents/DEMs-for-spatial-modelling.pdf 3. Àû ¡¦
°øÇбâ¼ú  | 
4p
age  
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1,200 ¿ø
µ¥ÀÌÅÍ ¸ðµ¨¸µ¿¡ ÀÖ¾î ¿ä±¸»çÇ× ¸í¼¼¸¦ ºÐ¼®ÇÏ¿© ER ¸ðµ¨·Î ±¸¼ºÇÏ´Â °³³äÀû ¼³°è¸¦ ¼öÇàÇÑ´Ù. »êÃâ¹°ÀÎ ERD¸¦ µ¥ÀÌÅ͸𵨠¼³°è ÅøÀÎ Toad for Data ModelerÀ» ÀÌ¿ëÇÏ¿© ÀÛ¼ºÇϽÿÀ / I. ¼·Ð II. º»·Ð 1. µ¥ÀÌÅÍ ¸ðµ¨¸µ ÀýÂ÷ 2. °³³äÀû ¼³°è ´Ü°èÀÇ ÀÌÇØ 3. °³³äÀû ¼³°èÀÇ »êÃâ¹°ÀÎ ERD ÀÛ¼º III. °á·Ð Âü°íÀÚ·á / I. ¼·Ð µ¥ÀÌÅͺ£À̽º ¼³°è´Â »ç¿ëÀÚ ¿ä±¸ »çÇ×À» ¿°µÎ¿¡ µÎ°í µ¥¡¦
°øÇбâ¼ú  | 
6p
age  
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2,000 ¿ø
µ¥ÀÌÅÍ ¸ðµ¨¸µ¿¡ ÀÖ¾î ¿ä±¸»çÇ× ¸í¼¼¸¦ ºÐ¼®ÇÏ¿© ER ¸ðµ¨·Î ±¸¼ºÇÏ´Â °³³äÀû ¼³°è¸¦ ¼öÇàÇÑ´Ù. »êÃâ¹°ÀÎ ERD¸¦ µ¥ÀÌÅ͸𵨠¼³°è ÅøÀÎ Toad for Data ModelerÀ» ÀÌ¿ëÇÏ¿© ÀÛ¼º / I. ¼·Ð II. º»·Ð 1. µ¥ÀÌÅÍ ¸ðµ¨¸µÀÇ ÀýÂ÷ 2. °³³äÀû ¼³°è ´Ü°èÀÇ ÀÌÇØ 3. °³³äÀû ¼³°èÀÇ »êÃâ¹°ÀÎ ERD ÀÛ¼º III. °á·Ð ¥³. Âü°í¹®Çå / I. ¼·Ð µ¥ÀÌÅͺ£À̽º ¼³°è´Â »ç¿ëÀÚÀÇ ¿ä±¸¸¦ °í·ÁÇÏ¿© µ¥ÀÌÅͺ£¡¦
°øÇбâ¼ú  | 
6p
age  
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2,000 ¿ø
[°øÇÐ][µðÁöÅÐ³í¸®È¸·Î] 4ºñÆ® µ¡¼À»¬¼À±â ȸ·Î ±¸Çö / ±âÃʺÎÅÍ ÀÀ¿ë±îÁö Verilog HDL - ´ÙÀ½Àº 4ºñÆ® µ¡¼À »¬¼À±âÀÇ ³í¸® ȸ·Î ÀÌ´Ù. 1. À§ÀÇ ³í¸® ȸ·Î¸¦ Gate level modeling ¹æ¹ýÀ» »ç¿ëÇÏ¿© Verilog Äڵ带 ÄÚµùÇϽÿÀ. Gate level modeling module Add_Subtraction input m; input [3:0] a,b; output [3:0] s; output c,v; wire [4:1] cn ; wire [3:0] n ; xor U1(n[0],m,b[0]);¡¦
°øÇбâ¼ú  | 
4p
age  
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1,200 ¿ø
[°øÇÐ][µðÁöÅÐ³í¸®È¸·Î] 4ºñÆ® µ¡¼À»¬¼À±â ȸ·Î ±¸Çö / ±âÃʺÎÅÍ ÀÀ¿ë±îÁö Verilog HDL - ´ÙÀ½Àº 4ºñÆ® µ¡¼À »¬¼À±âÀÇ ³í¸® ȸ·Î ÀÌ´Ù. 1. À§ÀÇ ³í¸® ȸ·Î¸¦ Gate level modeling ¹æ¹ýÀ» »ç¿ëÇÏ¿© Verilog Äڵ带 ÄÚµùÇϽÿÀ. Gate level modeling module Add_Subtraction input m; input [3:0] a,b; output [3:0] s; output c,v; wire [4:1] cn ; wire [3:0] n ; xor U1(n[0],m,b[0]);¡¦
°øÇбâ¼ú  | 
4p
age  
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1,200 ¿ø
[°øÇбâ¼ú] Rendering ¾Ë°í¸®ÁòÀÇ Á¾·ù - ¹Ì¸®º¸±â¸¦ Âü°í ¹Ù¶ø´Ï´Ù. / Rendering ¾Ë°í¸®ÁòÀÇ Á¾·ù Rendering ·»´õ¸µÀ̶õ Àå¸éÀ» À̹ÌÁö·Î ÀüȯÇÏ´Â °úÁ¤ÀÌ´Ù. Áï ÄÄÇ»ÅÍ ¼ÓÀÇ °¡»ó°ø°£Àº ·»´õ¸µÀ̶ó´Â °úÁ¤À» ÅëÇØ 2Â÷¿ø À̹ÌÁö·Î ¹Ù²î¾î ¿ì¸®¿¡°Ô º¸¿© Áø´Ù. Àü °úÁ¤ÀÌ ÄÄÇ»ÅÍ¿¡¼ ÀÌ·ç¾îÁöÁö¸¸ ½±°í ºü¸£°Ô ¿øÇÏ´Â °á°ú¸¦ ¾ò±â À§Çؼ´Â ÄÄÇ»ÅÍ°¡ ¾î¶² °úÁ¤À» ÅëÇؼ 3Â÷¿ø Àå¸éÀÌ¡¦
°øÇбâ¼ú  | 
4p
age  
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1,000 ¿ø