ÁýÀûȸ·Î(VLSI)ÀÇ ¼³°è °úÁ¤
VLSI ¼³°è
Àü¹ÝºÎ : Gate Level ¼³°è
ÈĹݺΠ: Layout µ¥ÀÌÅÍ »ý¼º
ÃÖ±ÙÀÇ ¼³°è
Àü¹ÝºÎ : µ¿ÀÛÀû ¼³°è(Behavioral Design) ` Gate Level ¼³°è
ÈĹݺΠ: Layout µ¥ÀÌÅÍ »ý¼º
2.1 »óÀ§ ·¹º§ ÇÕ¼º(High Level Synthesis)
2ºñÆ® ÀÔ·Â 4ºñÆ® Ãâ·Â
X(0) F(0)
X(1) F(1)
Y(0) F(2)
Y(1) F(3)
(a) ¼³°è »ç¾çÀÇ ºí·Ïµµ (b) ¼³°è »ç¾çÀÇ ÀÔÃâ·Â
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity exam is
port(X, Y : in std_logic_vector(1 downto 0);
F : out std_logic_vector(3 downto 0));
end exam;
architecture data_flow of exam is
begin
F `¡ë (X X) + (X Y) + (Y Y);
end data_flow;
(c) VHDL·Î Ç¥ÇöµÈ ¼³°è »ç¾ç
±×¸² 2.1.1 ¼³°è »ç¾ç
(a)
(b)
±×¸² 2.1.2 CDFG·Î Ç¥ÇöµÈ Áß°£ ÇüÅÂ
(a) ¸ÖƼ»çÀÌŬ¸µ ¡¦(»ý·«)
|