µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ¹× ½ÇÇè °á°úº¸°í¼
½ÇÇèÁ¦¸ñ
Latch, Flip-Flop, Shift Register
½ÇÇè¸ñÇ¥
1. SR NOR latch
2. Gated D latch(based on an SR NOR latch)
3. (Masterslave pulse-triggered) D flip-flop (with reset)
4. 4-bit shift register(using 4 D flip-flops)
½ÇÇè°á°ú
1. SR NOR latch
ÄÚµù
module (S,R,Q,Q_);
input S,R;
output Q,Q_;
nor (Q,R,Q_);
nor (Q_,S,Q);
endmodule
½Ã¹Ä·¹À̼Ç
S°¡ 1ÀÏ ¶§ Q´Â1 RÀÌ 1ÀÏ ¶§´Â Q_´Â 0 S,RÀÌ 0ÀÏ ¶§ ºÒº¯ S,RÀÌ 1ÀÏ ¶§´Â Á¤ÀǵÇÁö ¾Ê¾Æ ½Ã¹Ä·¹ÀÌ¼Ç ÇÏÁö ¾Ê¾Ò´Ù.
2. Gated D latch(based on an SR NOR latch)
ÄÚµù
module dl(D,C,Q,Q_);
input D,C;
output Q,Q_;
wire S,R;
wire ND;
not (ND,D);
and (R,ND,C);
and (S,D,C);
SR SR1 (S,R,Q,Q_);
endmodule
½Ã¹Ä·¹À̼Ç
C°¡ 1ÀÏ µÉ ¶§ DÀÇ ³»¿ëÀÌ Ãâ·ÂµÇ¸ç C°¡ 0ÀÏ ¶§´Â Ãâ·Â°ªÀÌ º¯ÇÏÁö ¾Ê´Â´Ù.
3. (Master&slave pulse-triggered) D flip-flop (with reset)
ÄÚµù
module dppr(D,C,R,Q,Q_);
input D,C,R;
output Q,Q_;
wire Q1,Q1_;
dl dl1 (AD,NC,Q1,Q1_);
dl dl2 (Q1,C,Q,Q_);
wire NR;¡¦(»ý·«)
|