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Schematic Level Design
1. Buck Converter simulation
Switching clock�쓽 operation speed
�몺 Transistor size, inductor/capacitor value瑜� 寃곗젙�븯湲�
Length(梨꾨꼸 湲몄씠) = 0.5um
Width(梨꾨꼸 �룺) = 50um
�몼 Capacitor 媛믪뿉 �뵲瑜� setting time怨� ripple 媛믪쓣 �븣�븘蹂대씪
C1= 0.1uF, 1uF, 10uF, 50uF
�몾 Switching clock�쓽 operation speed/duty cycle�뿉 Vout�쓽 �쁺�뼢
�씠怨� �씠�떎.
PER=100u[sec], f=10kHz, D=2%, Vout= �빟 5v
PER=10u[sec], f=100kHz, D=20%, Vout= �빟 14.5v
2. Boost Converter simulation Switching clock�쓽 operation speed
�몺 Transistor size, inductor/capacitor value瑜� 寃곗젙�븯湲�
Length(梨꾨꼸 湲몄씠) = 0.5um
Width(梨꾨꼸 �룺) = 50um
�몼 Capacitor 媛믪뿉 �뵲瑜� setting time怨� ripple 媛믪쓣 �븣�븘蹂대씪
C1= 0.1uF, 1uF, 10uF, 50uF
�몾 Switching clock�쓽 operation speed/duty cycle�뿉 Vout�쓽 �쁺�뼢
�씠怨� �씠�떎.
PER=100u[sec], f=10kHz, D=5%, Vout= �빟 45.5v
PER=10u[sec], f=100kHz, D=50%, Vout= �빟 75.5v
3. AC-DC / DC-DC Converter simulation
媛� node �뙆�삎�쓽 �솗�씤�쓣 �넻�븳 AC-DC�쓽 function怨� DC-DC function �솗�씤
�몺 PSPICE �쉶濡쒕룄
�몼 媛� n���(�깮�왂)
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schematic level design.hwp
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